AM79C970 datasheet(106/168 Pages) AMD

106 / 168 page

P R E L I M I N A R Y

AMD

1-973

Am79C970

linear burst before releasing the

bus.

As an example, if the linear burst

size is 4 transfers, and the num-

ber of wait states for the system

memory is 2, and the CLK period

is 30ns and the MAX time al-

lowed on the bus is 3

µs, then the

Burst Timer should be pro-

grammed for:

MAX_TIME– (((3+lbs) x w +

10 + lbs) x (CLK period))

µs – (((3 + 4) x 2 +10 + 4) x

(30 ns)) = 3

µs – (28 x 30 ns) = 3 –

0.84

µs = 2.16 µs.

Then, if the PCnet-PCIs Bus Ac-

tivity

Timer

times

out

after

2.16

µs when the PCnet-PCI

controller has completed all but

the last three transfers of a linear

burst, the PCnet-PCI controller

may take as much as 0.84

µs to

complete the bursts and release

the bus. The bus release will oc-

cur at 2.16 + 0.84 = 3

µs.

A value of ZERO in the DMABAT

CSR4 set to ONE will produce

single linear burst sequences per

bus master period when pro-

grammed for linear burst mode,

and will yield sets of 3 transfers

when not programmed for linear

burst mode.

The Bus Timer register is set to a

value of 00h after H_RESET or

S_RESET and is unaffected by

STOP.

Read/write accessible only when

STOP bit is set.

CSR84: DMA Address Register Lower

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 DMABAL

DMA Address Register.

This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABA register is undefined un-

til the first PCnet-PCI controller

DMA operation.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR85: DMA Address Register Upper

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 DMABAU

DMA Address Register.

This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABA register is undefined un-

til the first PCnet-PCI controller

DMA operation.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR86: Buffer Byte Counter

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–12

RES

Reserved, Read and written with

ones.

11–0 DMABC

DMA Byte Count Register. Con-

tains the two’s complement of the

current size of the remaining

transmit or receive buffer in

bytes. This register is incre-

mented by the Bus Interface Unit.

The DMABC register is unde-

fined until written.

Read/write accessible only when

STOP bit is set. These bits are

unaffected

H_RESET,

S_RESET or STOP.

CSR88: Chip ID Register Lower

Bit

Name

Description

31 – 28

Version. This 4-bit pattern is sili-

con-revision dependent.

27 – 12

Part number. The 16-bit code for

the PCnet-PCI controller is 0010

0100 0011 0000b.

AM79C970 Datasheet(PDF) 106 Page - Advanced Micro Devices

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