AM79C970 datasheet(105/168 Pages) AMD

105 / 168 page

AMD

P R E L I M I N A R Y

1-972

Am79C970

Combinations of watermark set-

tings and LINBC (BCR18, bits

2–0) settings must obey the

following relationship:

watermark (in bytes)

≥

LINBC (in bytes)

Combinations of watermark and

LINBC settings that violate this

rule

may

cause

unexpected

behavior.

7–0 DMATC[7:0]

DMA Transfer Counter. This

counter contains the maximum

allowable number of transfers to

system memory that the Bus In-

terface Unit will perform during a

single bus mastership period.

The DMA Transfer Counter is not

used to limit the number of trans-

fers during Descriptor transfers.

A value of ZERO will be inter-

preted as one transfer. During

H_RESET or S_RESET a value

of 16 is loaded in the DMA Trans-

fer

Counter.

The

value

DMATC is unaffected by the as-

sertion of the STOP bit. If the

DMAPLUS bit in CSR4 is set the

DMA Transfer Counter is dis-

abled.

When the DMA Transfer Counter

times out in the middle of a linear

burst, the linear burst will con-

tinue until a legal starting ad-

dress is reached, and then the

PCnet-PCI controller will relin-

quish the bus.

Therefore, if linear bursting is en-

abled, and the user wishes the

PCnet-PCI controller to limit bus

activity to desired_max transfers,

then the DMA Transfer Counter

should be programmed to a value

of:

DMA

Transfer

Counter =

(desired_max DIV

(length of burst in

transfers)) x length

of burst in transfers

where DIV is the operation that

yields the INTEGER portion of

the

÷ operation.

Read/write accessible only when

the STOP bit is set.

CSR82: Bus Activity Timer

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 DMABAT

Bus Activity Timer Register. If the

TIMER bit in CSR4 is set, this

allowable time that PCnet-PCI

controller will take up on the sys-

tem bus during FIFO data trans-

fers for a single DMA cycle. The

Bus Activity Timer Register does

not limit the number of transfers

during Descriptor transfers.

The DMABAT value is inter-

preted as an unsigned number

with a resolution of 0.1

µs. For in-

stance, a value of 51

µs would be

programmed with a value of 510.

If the TIMER bit in CSR4 is set,

DMABAT is enabled and must be

initialized

the

user.

The

DMABAT register is undefined

until written.

If the user has NOT enabled the

Linear Burst function and wishes

the PCnet-PCI controller to limit

bus activity to MAX_TIME micro-

seconds, then the Burst Timer

should be programmed to a value

of:

MAX_TIME– ((11 + 4w) x

(CLK period))

where w = wait states

If the user has enabled the Linear

Burst function and wishes the

PCnet-PCI controller to limit bus

activity to MAX_TIME microsec-

onds, then the Burst Timer

should be programmed to a value

of:

MAX_TIME– (((3+lbs) x w +

10 + lbs) x (CLK period))

where w = wait states and lbs =

linear burst size in number of

transfers per sequence

This is because the PCnet-PCI

controller may use as much as

one linear burst size plus three

transfers in order to complete the

AM79C970 Datasheet(PDF) 105 Page - Advanced Micro Devices

AM79C970 Datasheet(HTML) 105 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL