AM79C970 datasheet(108/168 Pages) AMD

108 / 168 page

P R E L I M I N A R Y

AMD

1-975

Am79C970

This register is always readable

and is cleared by H_RESET or

S_RESET or STOP.

A write to this register performs

an increment when the ENTST

bit in CSR4 is set.

CSR114: Receive Collision Count

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0

RCC

Receive Collision Count. Indi-

cates the total number of colli-

sions

encountered

the

receiver since the last reset of the

counter.

RCC will roll over to a count of

ZERO from the value 65535.

The RCVCCO bit of CSR4 (bit 5)

will be set each time that this

occurs.

The RCC value is read accessi-

ble at all times, regardless of the

value of the STOP bit. Write op-

erations are ignored.

RCC is

cleared

H_RESET

S_RESET or by setting the

STOP bit.

A write to this register performs

an increment when the ENTST

bit in CSR4 is set.

CSR122: Receive Frame Alignment Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–1

RES

Reserved locations, written as

ZEROs and read as undefined.

RCVALGN

Receive Packet Align. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e. DWORD (dou-

ble-word) aligned addresses). It

is important to note that this fea-

ture will only function correctly if

all receive buffer boundaries are

DWORD aligned and all receive

buffers have 0 MOD 4 lengths. In

order to accomplish the data

alignment, the PCnet-PCI con-

troller simply inserts two bytes of

random data at the beginning of

the receive packet (i.e. before the

ISO 8802-3 (IEEE/ANSI 802.3)

destination address field). The

MCNT field reported to the re-

ceive descriptor will not include

the extra two bytes.

RCVALGN is cleared by H_RE-

SET or S_RESET and is not af-

fected by STOP.

Read/write accessible only when

STOP bit is set.

CSR124: Test Register 1

Bit

Name

Description

This register is used to place the

PCnet-PCI

into

various

test

modes. Only the Runt Packet Ac-

cept is an user accessible test

mode. All other test modes are

for AMD internal use only.

ENTST must set before pro-

gramming

CSR124.

ENTST

must be reset after writing to

CSR124 before writing to any

other register.

All bits in this register are cleared

by H_RESET or S_RESET and

are not affected by STOP.

31–4

RES

Reserved locations. Written as

ZEROs and read as undefined.

RPA

Runt Packet Accept. This bit

forces the PCnet-PCI controller

receive logic to accept runt pack-

ets (packets shorter than 64

bytes). The state of the RPA bit

can be changed only when the

device is in the test mode (when

ENTST bit in CSR4 is set to

ONE).

To enable RPA, the user must

first write a ONE to the ENTST

bit. Next, the user must first write

a ONE to the RPA bit (CSR124,

bit 3). Finally, the user must write

a ZERO to the ENTST bit to take

the device out of test mode op-

eration. Once, the RPA bit has

been set to ONE, the device will

remain in the Runt Packet Accept

mode until the RPA bit is cleared

to ZERO.

2–0

RES

Reserved locations. Written as

ZEROs and read as undefined.

AM79C970 Datasheet(PDF) 108 Page - Advanced Micro Devices

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