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DS2196 Datasheet(PDF) 129 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 129 Page - Dallas Semiconductor |
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129 / 157 page  DS2196 129 of 157 Table 20-3: DEVICE ID CODES DEVICE 16-BIT NUMBER DS2196 0009 h HIGHZ All digital outputs of the DS2196 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. CLAMP All digital outputs of the DS2196 will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS2196 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Boundary Scan Register This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is 126 bits in length. Table 20-3 shows all of the cell bit locations and definitions. Bypass Register This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO. Identification Register The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic- Reset state. |
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