DS2196 datasheet(125/157 Pages) DALLAS

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DS2196

125 of 157

20.2TAP CONTROLLER STATE MACHINE

This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine.

Please see Figure 20.2 for details on each of the states described below.

TAP Controller

The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of

JTCLK.

Test-Logic-Reset

Upon power up of the DS2196, the TAP Controller will be in the Test-Logic-Reset state. The Instruction

Run-Test-Idle

The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and

Test registers will remain idle.

Select-DR-Scan

All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the

controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge

on JTCLK moves the controller to the Select-IR

Capture-DR

Data may be parallel-loaded into the Test Data registers selected by the current instruction. If the

instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test

DR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.

Shift-DR

The Test Data register selected by the current instruction will be connected between JTDI and JTDO and

will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test Register

selected by the current instruction is not placed in the serial path, it will maintain its previous state.

Exit1-DR

While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR

state, and terminate the scanning process. A rising edge on JTCLK with JTMS low will put the controller

in the Pause-DR state.

Pause-DR

Shifting of the test registers is halted while in this state. All Test registers selected by the current

instruction will retain their previous state. The controller will remain in this state while JTMS is low. A

rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.

DS2196 Datasheet(PDF) 125 Page - Dallas Semiconductor