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DS2196 Datasheet(PDF) 124 Page - Dallas Semiconductor

Part # DS2196
Description  T1 Dual Framer LIU
PDF  157 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2196 Datasheet(HTML) 124 Page - Dallas Semiconductor

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DS2196
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20.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
20.1DESCRIPTION
The DS2196 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP,
and IDCODE. See Figure 20-1 for a block diagram. The DS2196 contains the following items, which
meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 20-1: BOUNDARY SCAN ARCHITECTURE
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI
JTMS
JTCLK
JTRST
JTDO
+V
+V
Test Access Port
Controller
MUX
10K
10K
10K
Select
Output Enable



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