DS2196 datasheet(127/157 Pages) DALLAS

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DS2196

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Update-IR

The instruction code shifted into the instruction shift register is latched into the parallel output on the

falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the

current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle

state. With JTMS high, the controller will enter the Select-DR-Scan state.

Figure 20-2: TAP CONTROLLER STATE MACHINE

20.3INSTRUCTION REGISTER AND INSTRUCTIONS

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.

When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between

JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift the data

one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-

IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same

JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions

supported by the DS2196 with their respective operational binary codes are shown in Table 20-1.

Select

DR-Scan

Capture DR

Shift DR

Exit DR

Pause DR

Exit2 DR

Update DR

Select

IR-Scan

Capture IR

Shift IR

Exit IR

Pause IR

Exit2 IR

Update IR

Test Logic

Reset

Run Test/

Idle

DS2196 Datasheet(PDF) 127 Page - Dallas Semiconductor