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DS2196 Datasheet(PDF) 144 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 144 Page - Dallas Semiconductor |
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144 / 157 page  DS2196 144 of 157 AC CHARACTERISTICS – RECEIVE SIDE (0ºC to +70ºC; VDD = 3.135 to 3.465V for DS2196L) (-40ºC to +85ºC; VDD = 3.135 to 3.465V for DS2196LN) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES RCLKLO Period tLP 648 ns RCLKLO Pulse Width tLH tLL 250 250 324 324 ns ns 1 1 RCLKLO Pulse Width tLH tCL 200 200 324 324 ns ns 2 2 RCLKI Period tCP 648 ns RCLKI Pulse Width tCH tCL 75 75 ns ns RPOSI/RNEGI Set UP to RCLKI Falling tSU 20 ns RPOSI/RNEGI Hold From RCLKI Falling tHD 20 ns RCLKI Rise and Fall Times tR , tF 25 ns Delay RCLKLO to RPOSLO, RNEGLO Valid tDD 50 ns Delay RCLK to RSER, RLINK Valid tD1 50 ns Delay RCLK to RCHCLK, RFSYNC, RMSYNC, RCHBLK, RLCLK tD2 50 ns Delay WCLK/PCLK to WNRZ, PNRZ tD3 50 ns See Figures 22-8 to 22-9 for details. NOTES: 1. Jitter attenuator enabled in the receive path. 2. Jitter attenuator disabled in the receive path. |
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