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SLB128B Datasheet(PDF) 21 Page - National Semiconductor (TI) |
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SLB128B Datasheet(HTML) 21 Page - National Semiconductor (TI) |
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21 / 48 page ![]() Host Control Register Descriptions (Continued) Register Name: DEBUG_A Address Offset: 0Dh Default Value: See Description — Depends on pin state Access Method: Mixed Bit Description 1:0 DUAL (1:0), State of DUAL pin (Read Only) 00= SISO 01= SIDO 11= DIDO 2 PLLOCK (Read Only) 3 Reserved (Read Only) 7:4 Reserved (R/W) Register Name: RESERVED Address Offset: 0Eh–0Fh Default Value: 00h Access Method: R/W Bit Description 7:0 Reserved LVDS Interface TABLE 2. LVDS data bit naming convention X Y Z Description X=R Red X=G Green X=B Blue Y=1 Odd (First) Pixel Y=2 Even (Second) Pixel Z=0-7 LVDS bit number (not VGA controller LSB to MSB) www.national.com 21 |
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