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SLB128B Datasheet(PDF) 19 Page - National Semiconductor (TI) |
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SLB128B Datasheet(HTML) 19 Page - National Semiconductor (TI) |
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19 / 48 page ![]() Host Control Register Descriptions (Continued) Register Name: CFG1 Address Offset: 08h Default Value: 39h Access Method: R/W Bit Description 0 Soft Power Down; 0 = Power Down, 1 = Normal Operation 1 Reserved 2 BPASS (1 = bypass, 0 = non-bypass) This field is valid only when DUAL pin is 0V or 1⁄2V CC. Note: When image scaling is not required power savings can be achieved in bypass mode. 3 DSEL 0= Input clock is differential (recommended for clocks above 65 MHz), 1= input clock is single-ended 4 HEN (HSYNC enable) 0= HSYNC is transmitted as a fixed low, 1= HSYNC is same as input 5 VEN (VSYNC enable) 0= VSYNC is transmitted as a fixed low, 1= VSYNC is same as input 7:6 Reserved www.national.com 19 |
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