SLB128B datasheet(14/48 Pages) NSC

14 / 48 page

DS90C2501 Pin Description (Continued)

Pin Name

Pin No.

I/O Type

Description

OPTION SELECTION

A4M, A5M,

A6M, A7M

46, 44,

42, 40

O-LVDS

Negative LVDS differential data output for second pixel.

When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M.

For 6-bit color application, no connect for channel A3M.

When DUAL pin = 1⁄2V

CC, the first pixel going in D0–D11 will be coming out

of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M

to A7M. For 6-bit color application, no connect for channels A3M and A7M.

When DUAL pin = V

CC, the first pixel going in D0–D11 will be coming out of

A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M

to A7M. For 6-bit color application, no connect for channels A3M and A7M.

CLK1P

O-LVDS

Positive LVDS differential clock output.

CLK1M

O-LVDS

Negative LVDS differential clock output.

CLK2P

O-LVDS

Additional positive LVDS differential clock output pin. Identical to CLK1P. No

connect if not used.

CLK2M

O-LVDS

Additional negative LVDS differential clock output pin. Identical to CLK1M. No

connect if not used.

ID0, ID1, ID2,

ID3

57, 58,

59, 60

I-LVTTL 2.5

These four pins are used to select one out of 16 pre-determined LCD display

timing information. The values are from 0 to 15. This function requires support

from VBIOS or display driver. Tie these pins to GND when not in use. Tie

these four pins [ID3, ID2, ID1, ID0] to High or Low for selecting LCD panel.

ID0 is the LSB, and ID3 is the MSB. For example: 1000 will select the 9th

LCD panel.

A 4-bit register field [3:0] will be used to store the selected value for the host

to read. See PANEL field for more information.

ENAVDD

O-LVTTL 2.5

Output to control LCD panel power under software control. Typically, this

output is used with a power switch such as a FET circuit to control LCD panel

CC (Note 11).

ENABKL

O-LVTTL 2.5

Output to control LCD panel back light power under software control.

Typically, this output is used to control the enable on a backlight inverter

(Note 11).

MISCELLANEOUS/TEST

GPIO1,

GPIO2,

GPIO3

64, 63, 62

I/O-LVTTL 3V

General purpose inputs or outputs referenced to GND.

When the device is powered up, this pin defaults to an input.

When the scaler is in the power down state these signals are tri-state if

programmed as outputs (Note 11).

CLK_INV

114

I-LVTTL 2.5

This pin is used to invert the polarity of the incoming pixel CLK

(CLKINP/CLKINM). A logic 0 = Normal, Logic 1 = Invert.

RES2

I-LVTTL 2.5

This pin is used in production testing and should be tied to GND in normal

operation.

RES3

113

I-LVTTL 2.5

This pin is used in production testing and should be tied to GND in normal

operation.

RES4

100

I-LVTTL 2.5

This pin is used in production testing and should be tied to GND in normal

operation.

PWM

O-LVTTL 3V

This signal was provided for legacy support and is no longer required. This

pin should be left open in normal operation.

VSTALL

O-LVTTL 3V

This signal was provided for legacy support and is no longer required. This

pin should be left open in normal operation.

HIRQ

O-LVTTL 3V

This signal was provided for legacy support and is no longer required. This

pin should be left open in normal operation.

SLB128B Datasheet(PDF) 14 Page - National Semiconductor (TI)

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