Pin Name

Pin No.

I/O Type

Description

OPTION SELECTION

V

REF

83

I-ANALOG

This pin is never to be left floating and never tie to GND.

For LVTTL level data input, tie V

is set to LVTTL level.

For low voltage swing level data input, tie V

1

host interface) V

data is in low voltage swing mode.

Input data = logic High = V

Input data = logic Low = V

TST1, TST2,

TST3

19, 20, 85

I-LVTTL 2.5

These pins are used in production testing and should be tied to GND in

normal operation.

POWER (See Application Information for power supply decoupling requirements)

V

81, 82,

75, 77,

96, 119,

123, 125

PWR

Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL

inputs and digital circuitry.

GND/DGND

33, 73,

74, 76,

78, 79,

80, 84,

118, 122,

124

PWR

GND or DGND reference for 2.5V TTL inputs and digital circuitry.

V

121, 127

PWR

The V

During power up stage, voltage readings on these pins must be higher than

2.5V pins.

GND3V

120, 126,

128

PWR

Ground return pins for V

SPLLV

CC

87, 89

PWR

2.5V power supply pins for scaler PLL circuitry. It is not recommended to

share this power with PLLV

SPLLGND

86, 88, 90

PWR

Ground returns for scaler PLL circuitry.

PLLV

CC

92, 94

PWR

2.5V power supply pins for Tx PLL circuitry. It is not recommended to share

this power with SPLLV

PLLGND

91, 93, 95

PWR

Ground returns for Tx PLL circuitry.

LVDSV

CC

105, 109

PWR

Power supply pins for LVDS output drivers.

LVDSGND

104, 108

PWR

Ground return pins for LVDS output drivers.

LVDSV

101, 103,

107, 111

PWR

3V power supply pins for LVDS output drivers.

During power up stage, voltage readings on these pins must be higher than

2.5V pins.

LVDSGND3V

102, 106,

110, 112

PWR

Ground return pins for 3V LVDS outputs.

Note 11: When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least

0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gated externally

if the system design requires them to remain in the inactive logic “0” state during power-on.

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