Note 12: The lower half of the pixel is latched by the primary clock edge E1.

Note 15: D0 to D11 are clocked at the crossing point of CLKOUT+ and CLKOUT− when differential clock input is applied. This applies to D12 to D23 when DUAL

Note 16: Single-ended clock is not recommended for operation above 65MHz by GMCH vendor.

TABLE 9. 12-bit (two data per clock) input application data mapping with GMCH.

P0

P1

P2

P0L

P0H

P1L

P1H

P2L

P2H

Pin Name

Low

High

Low

High

Low

High

D11

G0[3]

R0[7]

G1[3]

R1[7]

G2[3]

R2[7]

D10

G0[2]

R0[6]

G1[2]

R1[6]

G2[2]

R2[6]

D9

G0[1]

R0[5]

G1[1]

R1[5]

G2[1]

R2[5]

D8

G0[0]

R0[4]

G1[0]

R1[4]

G2[0]

R2[4]

D7

B0[7]

R0[3]

B1[7]

R1[3]

B2[7]

R2[3]

D6

B0[6]

R0[2]

B1[6]

R1[2]

B2[6]

R2[2]

D5

B0[5]

R0[1]

B1[5]

R1[1]

B2[5]

R2[1]

D4

B0[4]

R0[0]

B1[4]

R1[0]

B2[4]

R2[0]

D3

B0[3]

G0[7]

B1[3]

G1[7]

B2[3]

G2[7]

D2

B0[2]

G0[6]

B1[2]

G1[6]

B2[2]

G2[6]

D1

B0[1]

G0[5]

B1[1]

G1[5]

B2[1]

G2[5]

D0

B0[0]

G0[4]

B1[0]

G1[4]

B2[0]

G2[4]

Note 17: Color notation: R = RED, G = GREEN, B = BLUE.

Note 18: Bit significance within a color: [7:0] = [MSB:LSB].

20004533

FIGURE 14. How Data is Latched in the DS90C2501

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