SLB128B datasheet(12/48 Pages) NSC

12 / 48 page

DS90C2501 Pin Description

Pin Name

Pin No.

I/O Type

Description

DVO INTERFACE

D0–D23

17, 16,

15, 14,

13, 12, 9,

8, 7, 6, 5,

4, 32, 31,

30, 29,

28, 27,

26, 25,

24, 23,

22, 21

I-LVTTL/ Low

Swing (See

REF signal

description

for more

information

on Low

Swing)

DVO Port RGB input data

When DUAL pin = GND inputs D0–D11 correspond to LVDS ports A0–A3.

When DUAL pin = 1⁄2V

CC, 1st pixel from D0–D11 corresponds to LVDS ports

A0–A3, 2nd pixel from D0–D11 corresponds to LVDS ports A4–A7.

When DUAL pin = V

CC, 1st pixel from D0–D11 corresponds to LVDS ports

A0–A3, 2nd pixel from D12–D23 corresponds to LVDS ports A4–A7.

Note: Ports refer to the corresponding differential LVDS pin pairs. The port A nomenclature should not

be confused with the serial interface slave address pins AO-A2.

I-LVTTL/ Low

Swing

Display Data Enable. When High, input pixel data is valid to DS90C2501

when R_FDE bit = High (default). See RFDE register field for more

information .

HSYNC

I-LVTTL/ Low

Swing

Display Horizontal Sync input control signal.

VSYNC

I-LVTTL/ Low

Swing

Display Vertical Sync input control signal.

CLKINP

I-LVTTL/ Low

Swing

Differential

“Positive” differential pixel clock input. A differential clock is recommended for

applications 65 MHz or higher.

CLKINM

I-LVTTL/ Low

Swing

Differential

“Minus” differential pixel clock input. A differential clock is recommended for

applications 65 MHz or higher.

HOST INTERFACE

RESETN

I-LVTTL 2.5

Active low RESET signal. Asserting RESETN will reset all internal logic and

clear the Host Interface registers.

S2CCLK

I-LVTTL3V

This is the clock line for the two-wire serial communication interface. Normally

a pull-up resistor is required in the system.

S2CDAT

I/O-LVTTL3V

This is the data line for two-wire serial communication interface. A Pull-up

resistor is normally required in the system.

MSEN

O-LVTTL 2.5

Interrupt signal. This is an open drain output, a pull-up resistor is required.

Please refer to MDI, RSEN, TSEL and MSEL register fields in Register Field

Definitions for more information. This signal requires support from host

software.

I-LVTTL 2.5

Power Down Signal. A logic “0” will place the device in power down mode per

Table 1 below.

When maximum power savings is desired, the PD pin or soft power down bit

(Reg 08h bit 0) should be used to power down the DS90C2501.

LVDS outputs of the device will be in TRI-STATE.

Scaling engine will be powered down, and retain all register values.

PLL will be powered down.

All data input pads will be powered down. V

REF circuit is powered down. The

two-wire serial communication interface remains active and all register

contents will be retained.

All GPIO pins will be disabled (tri-state if programmed as an output).

ENAVDD, ENABKL, PWM, VSTALL and HIRQ pins remain active and can be

accessed through the two-wire serial communication interface.

CLOCK

REFCLK1

I-LVTTL3V

Reference clock, — A 3V, 14.318 MHz clock is required for internal control

and timing. This clock must be stable when the DS90C2501 is powered-up.

SLB128B Datasheet(PDF) 12 Page - National Semiconductor (TI)

SLB128B Datasheet(HTML) 12 Page - National Semiconductor (TI)

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