TMS320VC5416 datasheet(31/98 Pages) TI1

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TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

The McBSP allows the multiple channels to be independently selected for the transmitter and receiver.

When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data

stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them.

Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of

particular channels for transmission and reception. All 128 channels in a bit stream consisting of a

maximum of 128 channels can be enabled.

Reserved

XMCME

XPBBLK

R/W

XPBBLK

XPABLK

XCBLK

Reserved

XMCM

R/W

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3-10. Multichannel Control Register (MCR1)

Reserved

RMCME

RPBBLK

R/W

RPBBLK

RPABLK

RCBLK

Reserved

RMCM

R/W

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3-11. Multichannel Control Register (MCR2)

The McBSP has two working modes:

• In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the

normal 32-channel selection is enabled (default).

• In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel

control register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME

= 1, twelve new registers ((R/X)CERC - (R/X)CERH) are used to enable the 128-channel selection.

The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.

Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported

by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is

configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or

as a slave.

Although the BCLKS pin is not available on the device PGE and GGU packages, the device is capable of

synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator

for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the

PCR to accommodate this option.

Reserved

XIOEN

RIOEN

FSXM

FSRM

CLKXM

CLKRM

R/W

SCLKME

CLKS STAT

DX STAT

DR STAT

FSXP

FSRP

CLKXP

CLKRP

R/W

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3-12. Pin Control Register (PCR)

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