TMS320VC5416 datasheet(43/98 Pages) TI1

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3.13 General-Purpose I/O Pins

3.13.1 McBSP Pins as General-Purpose I/O

TMS320VC5416

Fixed-Point Digital Signal Processor

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SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 3-12. DMA Synchronization Events (continued)

DSYN VALUE

DMA SYNCHRONIZATION EVENT

1110b

INT3 goes active

1111b

Reserved

The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on

the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt

sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the

McBSP. When the device is reset, the interrupts from these three DMA channels are deselected. The

INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3-13.

Table 3-13. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

BRINT2

BXINT2

BRINT1

BXINT1

01b

BRINT2

BXINT2

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

In addition to the standard BIO and XF pins, the device has pins that can be configured for

general-purpose I/O. These pins are:

• 18 McBSP pins

–

BCLKX0/1/2,

–

BCLKR0/1/2

–

BDR0/1/2

–

BFSX0/1/2

–

BFSR0/1/2

–

BDX0/1/2

• 8 HPI data pins

–

HD0-HD7

The general-purpose I/O function of these pins is only available when the primary pin function is not

required.

When the receive or transmit portion of a McBSP is in reset, its pins can be configured as

general-purpose inputs or outputs. For more details on this feature, see Section 3.8.

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