TMS320VC5416 datasheet(83/98 Pages) TI1

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th(BCKXH-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXH-BDXHZ)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

td(BFXL-BCKXL)

td(BFXL-BDXV)

td(BCKXL-BDXV)

tsu(BDRV-BCKXH)

th(BCKXH-BFXL)

LSB

MSB

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)

5416-120

5416-160

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high

2 – 6P(2)

th(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high

5 + 12P(2)

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = 0.5 * processor clock.

Table 5-29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1)

5416-120

5416-160

PARAMETER

UNIT

MASTER(2)

SLAVE

MIN

MAX

MIN

MAX

th(BCKXH-BFXL)

Hold time, BFSX low after BCLKX high(3)

T – 3

T + 4

td(BFXL-BCKXL)

Delay time, BFSX low to BCLKX lowTNote9543(4)

D – 4

D + 3

td(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid

– 4

6P + 2(5)

10P + 17(5)

Disable time, BDX high impedance following last data bit from

tdis(BCKXH-BDXHZ)

D – 2

D + 3

BCLKX high

Disable time, BDX high impedance following last data bit from

tdis(BFXH-BDXHZ)

2P – 4(5)

6P + 17(5)

BFSX high

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4P + 2(5)

8P + 17(5)

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

T = BCLKX period = (1 + CLKGDV) * 2P

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even

(3)

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input

on BFSX and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP

CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP

(4)

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the

master clock (BCLKX).

(5)

P = 0.5 * processor clock.

Figure 5-26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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TMS320VC5416 Datasheet(PDF) 83 Page - Texas Instruments

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