TMS320VC5416 datasheet(59/98 Pages) TI1

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5.4.2

Multiply-By-N Clock Option (PLL Enabled)

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

X2/CLKIN

CLKOUT

(see Note A)

td(CI-CO)

tw(COL)

tr(CI)

Unstable

tw(CIH)

tw(CIL)

TMS320VC5416

Fixed-Point Digital Signal Processor

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SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate

the internal machine cycle. The selection of the clock mode and the value of N is described in Section 3.10.

Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to the

TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for detailed

information on programming the PLL.

When an external clock source is used, the external frequency injected must conform to specifications listed in

Table 5-5.

Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5-4).

Table 5-5. Multiply-By-N Clock Option Timing Requirements

5416-120

5416-160

Unit

MIN

MAX

Integer PLL multiplier N (N = 1-15)(1)

200

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.5(1)

100

PLL multiplier N = x.25, x.75(1)

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

tw(CIL)

Pulse duration, X2/CLKIN low

tw(CIH)

Pulse duration, X2/CLKIN high

(1)

N is the multiplication factor.

Table 5-6. Multiply-By-N Clock Option Switching Characteristics

5416-120

5416-160

PARAMETER

Unit

MIN

TYP

MAX

MIN

TYP

MAX

tc(CO)

Cycle time, CLKOUT

8.33

6.25

td(CI-CO)

Delay time, X2/CLKIN high/low to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H – 2

H + 1

H – 2

H + 1

tw(COH)

Pulse duration, CLKOUT high

H – 2

H + 1

H – 2

H + 1

Transitory phase, PLL lock-up time

The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as

00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.

Figure 5-4. Multiply-By-One Clock Timing

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