TMS320VC5416 datasheet(41/98 Pages) TI1

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3.12.6 DMA in Autoinitialization Mode

3.12.7 DMA Transfer Counting

3.12.8 DMA Transfer in Doubleword Mode

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA

registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA,

DMGDA, DMGCR, and DMGFR). Autoinitialization allows:

• Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfers, but with the reload registers, it can reinitialize these values

for the next block transfer any time after the current block transfer begins.

• Repetitive operation:The CPU does not preload the reload register with new values for each block

transfer but only loads them on the first block transfer.

The DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its

own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0,

DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and

DMGFR1, etc.

To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown

in Figure 3-19.

FREE

AUTOIX

DPRC[5:0]

IOSEL

DE[5:0]

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3-19. DMPREC Register

Table 3-10. DMA Reload Register Selection

AUTOIX

DMA RELOAD REGISTER USAGE IN AUTO INIT MODE

0 (default)

All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0

Each DMA channel uses its own set of reload registers

The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit

fields that represent the number of frames and the number of elements per frame to be transferred.

• Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum

number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented

upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit

counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1.

A frame count of 0 (default value) means the block transfer contains a single frame.

• Element count. This 16-bit value defines the number of elements per frame. This counter is

decremented after the read transfer of each element. The maximum number of elements per frame is

65536 (DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter

is reloaded with the DMA global count reload register (DMGCR).

Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically

updated following each transfer. In this mode, each 32-bit word is considered to be one element.

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