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TMS320VC5416 Datasheet(PDF) 86 Page - Texas Instruments

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Part # TMS320VC5416
Description  Fixed-Point Digital Signal Processor
PDF  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320VC5416 Datasheet(HTML) 86 Page - Texas Instruments

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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
www.ti.com
Table 5-33. HPI8 Mode Switching Characteristics
5416-120
5416-160
PARAMETER
UNIT
MIN
MAX
ten(DSL-HD)
Enable time, HD driven from DS low
0
10
ns
Case 1a: Memory accesses when DMAC is active
36P + 10 –
in 32-bit mode and tw(DSH) < 36P
(1)
tw(DSH)
Case 1b: Memory accesses when DMAC is active
10
in 32-bit mode and tw(DSH) ≥ 36P
(1)
Case 1c: Memory accesses when DMAC is active
18P + 10 –
in 16-bit mode and tw(DSH) < I8P
(1)
tw(DSH)
Delay time, DS low to HD valid
td(DSL-HDV1)
Case 1d: Memory accesses when DMAC is active
ns
for first byte of an HPI read
10
in 16-bit mode and tw(DSH) ≥ I8P
(1)
Case 2a: Memory accesses when DMAC is inactive
10P + 10 –
and tw(DSH) < 10P
(1)
tw(DSH)
Case 2b: Memory accesses when DMAC is inactive
10
and tw(DSH) ≥ 10P
(1)
Case 3: Register accesses
10
td(DSL-HDV2)
Delay time, DS low to HD valid for second byte of an HPI read
10
ns
th(DSH-HDV)R
Hold time, HD valid after DS high, for a HPI read
0
ns
tv(HYH-HDV)
Valid time, HD valid after HRDY high
2
ns
td(DSH-HYL)
Delay time, DS high to HRDY low(2)
8
ns
Case 1a: Memory accesses when DMAC is active
18P + 6
in 16-bit mode(1)
Case 1b: Memory accesses when DMAC is active
36P + 6
Delay time, DS high to HRDY
in 32-bit mode(1)
td(DSH-HYH)
ns
high(2)
Case 2: Memory accesses when DMAC is
10P + 6
inactive(1)
Case 3: Write accesses to HPIC register(3)
6P + 6
td(HCS-HRDY)
Delay time, HCS low/high to HRDY low/high
6
ns
td(COH-HYH)
Delay time, CLKOUT high to HRDY high
9
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
6
ns
Delay time, CLKOUT high to HDx output change. HDx is configured as a
td(COH-GPIO)
5
ns
general-purpose output
(1)
DMAS stands for direct memory access controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
(2)
The HRDY output is always high when the HCS input is high, regardless of DS timings.
(3)
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
Electrical Specifications
86
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