AD9261 datasheet(7/29 Pages) AD

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AD9261

Rev. 0 | Page 6 of 28

SWITCHING SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,

unless otherwise noted.

Table 5.

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK INPUT (USING CLOCK MULTIPLIER)

Conversion Rate

Full

160

MSPS

CLK± Period

Full

6.25

CLK± Duty Cycle

Full

CLOCK INPUT (DIRECT CLOCKING)

Conversion Rate

Full

608

640

672

MSPS

CLK± Period

Full

1.49

1.5625

1.64

CLK± Duty Cycle

Full

DATA OUTPUT PARAMETERS

Output Data Rate

Full

168

MSPS

DCO to Data Skew (tSKEW)2

Full

Sample Latency

Full

960

Cycles

WAKE-UP TIME3

Full

Power Down Power

Full

μs

Standby Power

Full

μs

Sleep Power

Full

μs

OUT-OF-RANGE RECOVERY TIME

Full

960

Cycles

SERIAL PORT INTERFACE4

SCLK Period

Full

SCLK Pulse Width High Time (tSHIGH)

Full

SCLK Pulse Width Low Time (tSLOW)

Full

SDIO to SCLK Setup Time (tSDS)

Full

SDIO to SCLK Hold Time (tSDH)

Full

CSB to SCLK Setup Time (tSS)

Full

CSB to SCLK Hold Time (tSH)

Full

1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2 Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load.

3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 μF capacitor on VREF and CFILT.

4 See Figure 50 and the Serial Port Interface (SPI) section.

Timing Diagram

DCO

D0 TO D15

tSKEW

Figure 2. Timing Diagram

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