AD9261 datasheet(22/29 Pages) AD

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AD9261

Rev. 0 | Page 21 of 28

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Figure 48. 5 MHz Signal Bandwidth, 160 MSPS

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Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS

DIGITAL OUTPUTS

Digital Output Format

The AD9261 offers a variety of digital output formats for ease of

system integration. The digital output consists of 16 data bits and

an output clock signal (DCO) for data latching. The data bits can

be configured for offset binary, twos complement, or Gray code

by writing to Register 0x14[1:0]. In addition, the voltage swing of

the digital outputs can be configured to 3.3 V TTL levels or a

reduced voltage swing of 1.8 V by accessing Register 0x14[7].

When 3.3 V voltage levels are desirable, the DRVDD power

supply must be set to 3.3 V.

Overrange (OR) Condition

The OR pin serves as an indicator for an overrange condition. The

OR pin is triggered by in-band signals that exceed the full-scale

range of the ADC. In addition, the AD9261 possesses out-of-

band gain above 10 MHz; therefore, a large out-of-band signal

may trip an overrange condition.

The OR pin is a synchronous output that is updated at the out-

put data rate. Ideally, OR should be latched on the falling edge of

DCO to ensure proper setup-and-hold time. However, because

an overrange condition typically extends well beyond one clock

cycle—that is, it does not toggle at the DCO rate—data can

usually be successfully detected on the rising edge of DCO or

monitored asynchronously.

The AD9261 has two trip points that can trigger an overrange

condition: analog and digital. The analog trip point is located

in the modulator, and the second trip point is in the digital

engine. In normal operation, it is possible for the analog trip

point to toggle the OR pin for a number of clock cycles as the

analog input approaches full scale. Because the OR pin is a pulse-

width modulated (PWM) signal, as the analog input increases

in amplitude, the duration of overrange pin toggling increases.

Eventually, when the OR pin is high for an extended period of

time, the ADC is overloaded, and there is little correspondence

between analog input and digital output.

The second trip point is in the digital block. If the input signal

is large enough to cause the data bits to clip to the maximum

full-scale level, an overrange condition occurs. The overrange

trip point can be adjusted by specifying a threshold level.

Table 19 shows the corresponding threshold level in dBFS vs.

is set. In the case where 0x111[5:0] is set to all 0s, the threshold

level is set to the maximum code of 32,76710. This feature

provides a means of reporting the instantaneous amplitude as it

crosses a user-provided threshold. This gives the user a sense

for the signal level without needing to perform a full power

measurement.

The user has the ability to select how the overrange conditions

are reported, and this is controlled through Register 0x111 via

AUTORST, OR_IND, and ORTHRESH (see Table 20). By

enabling the AUTORST bit, Register 0x111[7], if an overrange

occurs, the ADC automatically resets itself. The OR pin remains

high until the automatic reset has completed. If an analog trip

occurs, the modulator resets itself after 16 consecutive clock

cycles of overrange.

If the AD9261 is used in a system that incorporates automatic

gain control (AGC), the OR signal can be used to indicate that

the signal amplitude should be reduced. This may be particularly

effective for use in maximizing the signal dynamic range if the

signal includes high occurrence components that occasionally

exceed full scale by a small amount.

TIMING

The AD9261 provides a data clock out (DCO) pin to assist

in capturing the data in an external register. The data outputs

are valid on the rising edge of DCO, unless changed by setting

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