AD9261 datasheet(26/29 Pages) AD

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AD9261

Rev. 0 | Page 25 of 28

MEMORY MAP

Table 23. Memory Map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPI Port Config

0x00

LSBFIRST

SOFTRESET

LSBFIRST

Chip ID

0x01

CHIPID[7:0]

Chip Grade

0x02

CHILDID[2:0]

Power Modes

0x08

PWRDWN[1:0]

PLLENABLE

0x09

PLLENABLE

PLL

0x0A

PLLLOCKED

PLLAUTO

PLLMULT[5:0]

Analog Input

0x0F

BW[1:0]

Output Modes

0x14

DRVSTD

Interleave

OUTENB

OUTINV

Format[1:0]

Output Adjust

0x15

DRVSTR33[1:0]

DRVSTR18[1:0]

Output Clock

0x16

DCOINV

Reference

0x18

EXTREF

Output Data

0x101

KOUT[5:0]

Overrange

0x111

AUTORST

OR_IND

ORTHRESH[5:0]

MEMORY MAP DEFINITIONS

Table 24. Memory Map Definitions

Address

Bit(s)

Mnemonic

Default

Description

SPI Port Config

0x00

6, 1

LSBFIRST

0: serial interface uses MSB first format

1: serial interface uses LSB first format

5, 2

SOFTRESET

1: default all serial registers except 0x00, 0x09, and 0x0A

Chip ID

0x01

[7:0]

CHIPID

0x26

0x26: AD9261

Chip Grade

0x02

[5:4]

CHILDID

0x00: 10 MHz bandwidth

Power Modes

0x08

[1:0]

PWRDWN

0x0: normal operation

0x1: power-down (local)

0x2: standby (everything except reference circuits)

0x3: sleep

PLLENABLE

0x09

PLLENABLE

1: enable PLL

PLL

0x0A

PLLLOCKED

0: PLL is not locked

1: PLL is locked

PLLAUTO

1: PLL autoband enabled

[5:0]

PLLMULT

See Table 10

Analog Input

0x0F

[6:5]

0x0: 10 MHz

0x1: 5 MHz

0x2: 2.5 MHz

0x3: 10 MHz

Output Modes

0x14

DRVSTD

0: 3.3 V

1: 1.8 V

Interleave

1: interleave both channels onto D[15:0]

OUTENB

1: data outputs tristated

OUTINV

1: data outputs bitwise inverted

[1:0]

Format

0: offset binary

1: twos complement

2: Gray code

3: offset binary

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