 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9261 Datasheet(PDF) 18 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9261 Datasheet(HTML) 18 Page - Analog Devices |
|
|
18 / 29 page  AD9261 Rev. 0 | Page 17 of 28 Internal PLL Clock Distribution The alternative clocking option available on the AD9261 is to apply a low frequency reference clock and use the on-chip clock multip- lier to generate the high frequency fMOD rate. The internal clock architecture is shown in Figure 45. PHASE DETECTOR DIVIDER PLL MULT 0x0A[5:0] CLK+/CLK– MODULATOR CLOCK 640MSPS PLLENABLE 0x09[2] ÷N LOOP FILTER 1.28GHz VCO PLL ÷2 Figure 45. Internal Clock Architecture The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the reference clock input multiplied by N fVCO = (CLK±) × (N) where N is the PLL multiplication (PLLMULT) factor. The Σ-Δ modulator clock frequency, fMOD, is equal to fMOD = fVCO ÷ 2 The reference clock, CLK±, is limited to 30 MHz to 160 MHz when configured to use the on-chip clock multiplier. Given the input range of the reference clock and the available multiplication factors, the fVCO is approximately 1280 MHz. This results in the desired fMOD rate of 640 MHz with a 50% duty cycle. Before the PLL enable (PLLENABLE) register bit is set, the PLL multiplication factor should be programmed into Register 0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and reports a locked state in Register 0x0A[7]. If the PLL multiplica- tion factor is changed, the PLL enable bit should be reset and set again. Some common clock multiplication factors are shown in Table 11. The recommended sequence for enabling and programming the on-chip clock multiplier is summarized in Table 9. Table 9. Sequence for Enabling and Programming the PLL Step Procedure 1 Apply a reference clock to the CLK± pins. 2 Program the PLL multiplication factor in Register 0x0A[5:0]. See Table 10. 3 Enable the PLL; Register 0x09 = 04 (decimal). 4 Enable the PLL autoband select. 5 Initiate an SRC reset; Register 0x101[5:0] = 0. 6 Set SRC to the desired value via Register 0x101[5:0]. Table 10. Internal PLL Multiplication Factors 0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N) 1 8 33 32 2 8 34 34 3 8 35 34 4 8 36 34 5 8 37 34 6 8 38 34 7 8 39 34 8 8 40 34 9 9 41 34 10 10 42 42 11 10 43 42 12 12 44 42 13 12 45 42 14 14 46 42 15 15 47 42 16 16 48 42 17 17 49 42 18 18 50 42 19 18 51 42 20 20 52 42 21 21 53 42 22 21 54 42 23 21 55 42 24 24 56 42 25 25 57 42 26 25 58 42 27 25 59 42 28 28 60 42 29 28 61 42 30 30 62 42 31 30 63 42 32 32 64 42 External PLL Control At power-up, the serial interface is disabled until the first serial port access. If the serial interface is disabled, the PLLMULTx pins control the PLL multiplication factor. The five PLLMULTx pins (Pin 32 to Pin 36) offer all the available multiplication factors. If all PLLMULTx pins are tied high, the PLL is disabled and the AD9261 assumes the high frequency modulator clock rate that is applied to the CLK± pins. Table 12 shows the relation- ship between PLLMULTx pins and the PLL multiplication factor. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
