TLFD600 datasheet(28/36 Pages) TI1

28 / 36 page

TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PROGRAMMING INFORMATION

GPR-D – GPIO data register

Address: 01001b

Contents at reset: 00000000b

Reserved

GPOD[5]

GPOD[4]

GPOD[3]

GPOD[2]

GPOD[1]

GPOD[0]

Table 10. GPIO Control Table

BIT NAME

Description

Reserved

GPOD[5]

0/1

GPO5 = 0/1

GPOD[4]

0/1

GPO4 = 0/1

GPOD[3]

0/1

GPO3 = 0/1

GPOD[2]

0/1

GPO2 = 0/1

GPIOD[1]

0/1

GPIO1 = 0/1 when GPIO1 is configured as output. See

Note 7.

GPIOD[0]

0/1

GPIO0 = 0/1 when GPIO1 is configured as output. See

Note 7.

NOTE 7: It is recommended to write zeroes to GPIO1 and GPIO0 if they are configured as inputs.

FMR – frequency mode register

Address: 01010b

Contents at reset: 00000000b

Reserved

SLTXBW

Reserved

SLRXBW

DBLTXS

TOGMOD

Table 11. FMR Control Table

BIT NAME

DESCRIPTION

Reserved

SLTXBW

TX LPF bandwidth 125 kHz

SLTXBW

TX LPF bandwidth 138 kHz

Reserved

SLRXBW

Reserved

DBLTXS

TX FSR sampling at 552 Ksps

DBLTXS

TX FSR sampling at 276 Ksps

TOGMOD

Work mode (G.lite/full rate) opposite of that selected by

MODESEL pin

TOGMOD

Work mode (G.lite/full rate) as selected by MODESEL pin

NOTE 8: Table 12 shows the effect of MODESEL pin (pin 10) and TOGMOD bit (FMR[0]).

TLFD600 Datasheet(PDF) 28 Page - Texas Instruments

TLFD600 Datasheet(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL