TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

16

POST OFFICE BOX 655303

DPLL description (continued)

The position of the first jittering SCLK cycle is calculated by using the following equation:

(NCO_DIV_DLY [7 : 0]

) 1)

16

) 7

The following jittering SCLKs will separate by 16 SCLK from the first one if NCO_DELTA[3:0] is more than one.

Figures 16 and 17 shows the timing of SCLK at the following setting:

NCO_DELTA [7:4] = – 1

NCO_DELTA [3:0] = 2

NCO_DIV_DELAY = 2

64 SCLKs

16 SCLKs

P

P

P

FSR

FSX

SDR

SCLK

Data

P

P

P

P

P

P

P

P

P

Data

Don’t care

Don’t care

S

P

The 9th SCLK duty cycle change

to 14ns(1) and 7ns(0)

15th

0

Secondary Command Request

Command to Program

NCO_DIV_DELAY

Start counting

Figure 16. DPLL Operation Example (FSR = 552 kHz and FSX = 2208 kHz)

NOTE: The situation will be the same for FSR = 276 kHz