TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

6

POST OFFICE BOX 655303

transmit channel(continued)

The line driver is also integrated in the TX channel. It helps optimize system components, board size, and cost.

The driver is powered by a 12-V, supply and has a fixed gain of 15.7 dB. This provides a maximum drive of 18.2

Vp-p differential output when the input is 3 Vp-p (maximum input range). Thus, a transformer with 1:2 ratio is

needed for ADSL modem application. The minimum load that the driver can drive is 33

Ω, thus, making the part

coexist with up to 3 HPNA devices connected to the same line.

The line driver has separate input and output pins. This gives flexibility to add additional filters in the transmit

path. The line driver can be powered down by register programming.

The TXOUTP and TXOUTM pins must be ac-coupled to the DRIVERINP and DRIVERINM through 0.1-

µF

capacitors, as the common mode voltage on the pin pairs are different (1.5 Vdc on TXOUTP/M and 6 Vdc on

DRIVERINP/M). They must not be dc-coupled.

receive channel

The receiver channel consists of a coarse programmable gain amplifier (CPGA), analog high-pass and

low-pass filters, two programmable gain amplifiers, ADC, and a digital filter. In addition, it adds an equalizer to

obtain maximum system performance. The receive signal is processed in a fully differential way.

The ADC in the receiver channel is a 4.416-MHz, 14-bit converter. The interface transfer rate is either 1104 kHz

or 2208 kHz, depending on the mode at operation. 1104 kHz is used for G.lite mode, and 2208 kHz is used for

full rate mode. The mode can be selected either by pin 10 (MODESEL) or register programming. The related

cutoff frequency of analog and digital filters is also changed with the mode selection.

The high-pass analog filter is used to reject the near end echo and maximize the dynamic range of the ADC.

The high-pass filter edge is programmable and is controlled by bit D2 of FMR register. D2 = 0 selects a 180-kHz

(

±3.5%) pole, while D2 = 1 selects a 168-kHz (±3.5%) pole.

After the high-pass filtering stage, the receiver channel has two PGAs. A 552-kHz/1104-kHz low-pass filter with

a 25-dB shape equalizer goes after them and antialiases the analog signal before it goes through the ADC. The

RX low pass filter is also designed to reject the out-of-band HPNA signal. Next is a fine gain adjustment PGA

of 0 to 9 dB, in 1-dB steps. All the RX PGAs and equalizer are controlled via the register programming.

External components are required to implement CPGA function. Suggested components and connection are

shown in the Figure 1.

R = 732

Ω

C = 680 pF

R = 732

Ω

C = 680 pF

RXINP

RXINM

Figure 1. External Components for RXINP and RXINM

The configuration of Figure 1 gives the following setting for CPGA: –9dB to 9dB in 6 dB/steps and 9 dB to 30

dB in 3 dB/steps. The CPGA gain range is controlled by external resistors (732

Ω shown in Figure 1). The cut-off

frequency of the HPF is controlled by external resistors (R) and capacitors (C). To keep the cutoff frequency

of the first HPF unchanged, R

× C need to be constant.