TLFD600 datasheet(4/36 Pages) TI1

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TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AMP1INM

AMP2INM

Auxiliary amplifier 1 and 2 negative input

AMP1INP

AMP2INP

Auxiliary amplifier 1 and 2 positive input

AMP1OUTM

AMP2OUTM

Auxiliary amplifier 1 and 2 negative output

AMP1OUTP

AMP2OUTP

Auxiliary amplifier 1 and 2 positive output

ANA_TST

External resistor connection input. A 15-k

Ω (±5%) resistor must be connected between

ANA_TST and analog ground.

AVDD_DRIVER

Analog power supply for TX driver (12 V)

AVDD_REF

Reference analog supply

AVDD_RX

38, 53

RX channel filter analog supply

AVDD_TX

TX channel analog supply

AVSS_DRIVER

TX driver analog supply return (analog ground)

AVSS_REF

Reference analog supply return (analog ground)

AVSS_RX

39, 54

RX channel filter analog supply return (analog ground)

AVSS_TX

TX channel analog supply return (analog ground).

CLK1OUT

Generates clock of frequency MCLKx4/n, where n is 7 or 9. Value of n is selected by CLK1SEL.

CLK2OUT

Generates clock of frequency MCLKx4/34.5.

CLK1SEL

Selects whether n = 7 or 9 for CLK1OUT. For CLK1SEL = 0, n = 6.

CLKOUT_EN

Enable CLK1OUT and CLK2OUT when CLKOUT_EN is high. The default state of

CLKOUT_EN is low.

COMPDAC1

TX channel decoupling cap input A. Add a 1-

µF ceramic capacitor to analog power supply.

COMPDAC2

TX channel decoupling cap input B. Add a 1-

µF ceramic capacitor to analog power supply.

DRIVERINM

TX channel driver negative input. A 0.1-

µF capacitor is needed when it connects to TXOUTM.

DRIVERINP

TX channel driver positive input. A 0.1-

µF capacitor is needed when it connects to TXOUTP.

DRIVEROUTM

TX channel driver negative output

DRIVEROUTP

TX channel driver positive output

DVDD

Digital power supply

DVDD_IO

Power supply for digital I/O buffer

DVDD_RX

RX channel digital power supply

DVSS

23, 24, 37

Digital ground

DVSS_IO

Digital I/O buffer supply return (digital ground)

DVSS_RX

RX channel digital supply return (digital ground)

FSX

Serial port frame sync transmit signal

FSR

Serial port frame sync receive signal

GPIO0

GPIO1

I/O

General-purpose I/O

GPO2 – 5

33 – 36

General-purpose output

MCLKIN/PLLCLKIN

Master clock input for normal mode (use off-chip VCXO) and DPLL (use fix input clock and

change clock phase by control register) mode. The required input clock frequency is

35.328 MHz

±50 ppm.

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