TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

7

POST OFFICE BOX 655303

receive channel (continued)

For example: If R = 2063

Ω, the external capacitor (C) needs to be 240 pF. The gain setting for CPGA changes

to the following range: –18 dB to 0 dB in 6 dB/steps and 0 dB to 21 dB in 3 dB/steps. The 9 dB shifting is calculated

by using the following equation:

20

log

2063

732

+ 9dB

The linearity of the external capacitors and inductors is very important to the whole RX channel performance.

Capacitors of NPO grade or better need to be used.

clock control-VCXO

A 12-bit, serial DAC is used to control the external 35.328-MHz VCXO (voltage control oscillator) that provides

the system clock to the CODEC. Two 8-bit registers, (each 2s complement) VCRM and VCRL, are used to

generate the 12-bit control code. This implies using two 8-bits to obtain a 12-bit code. The VCRM register

occupies the most significant 8 bits in the 12-bit code and the lower 4 bits of the VCRL register (VCRL[3:0]) are

used for the low 4 bits of the 12-bit code. The internal DAC register is updated only when VCRL is programmed.

Table 1 shows some representative analog outputs.

Table 1. VCXO DAC Digital-Analog Mapping

OPERATION

HEX RESULT

ANALOG OUTPUT

COMMENTS

VCRM[7:0]

× 24 + VCRL[3:0]

0x800

0 V

Min scale

0x801

∆V

Just above min

…

…

…

0xFFF

2047

∆V

Just below mid

0x000

2048

∆V

Mid scale

0x001

2049

∆V

Just above mid

…

…

…

0x7FE

4094

∆V

Just below max

0x7FF

4095

∆V

Max scale

Where step-size,

∆ = (3/4095) V.

1. The analog output is computed as follows: ((VCRM[7:0]

2. Step-size

∆ is computed as follows: 0 x 800 (–2048 decimal) is 0 V and 0x7FF (2047 decimal) is 3 V. Thus,

∆ = (3 – 0) / (2047 – (–2048)) V = (3/4095) V

clock generation

The clock generation block provides the necessary clocks for the different functional blocks on the board with

minimum skew and jitters. This is closely dependent on the performance of the external VCXO. The external

VCXO specification is:

The on-chip clocks are shown in Table 2. CLK1OUT and CLK2OUT can be used as general clock sources, or

they can be disabled if they are not used.