TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

15

POST OFFICE BOX 655303

power down

Both hardware and software power-down modes are provided. Some function blocks can be powered down

individually according to the control register setting. A logic-zero on the PWRDWN pin will completely shut down

the codec.

device initialization time

RESET must be held at least 20

µs after power up. To reset the reference circuit and registers requires 100 ms.

When the chip is woken up from hardware power-down mode, it takes 100 ms to reset the reference circuit

before the chip works in normal mode. When the chip is woken up from software power-down mode, only 20

µs

is needed before valid data comes out (reference must be kept on). Register values will not change in either

wake-up operation.

DPLL description

As an alternative to the VCXODAC and VCXO, an off-chip crystal oscillator (XO) followed by an on-chip digital

PLL is also implemented. See Figure 15 for the internal functional block diagram. The input clock (35.328 MHz)

goes to a programmable frequency-divider to generate the sampling clock for the ADC and DAC. By changing

the divide ratio, the phase of sampling clock for ADC and DAC channels can be adjusted. therefore, setting the

PLLSEL (pin 26) high to enable the DPLL mode.

The default value of register NCO_DEF is 64, and it can only be changed internally. With the 35.328-MHz input

clock, the output frequency of PLL is 4 x 35.328 = 141.312 MHz. To obtain an ADC clock (ADCCLK) of 4.416

MHz, the divide ratio (controlled by register NCO_DEF and NCO_DELTA) needs to be 32. Increasing or

decreasing this ratio (for example, 32.5 or 31.5) temporally can effect the phase of 4.416-MHz sampling clock.

See the following example for details.

+

PLL (X4)

NCO_DEF

×2

NCO_DIV_DELAY

NCO_DELTA

[7:4]

NCO_DELTA

[3:0]

MCLKIN/

PLLCLKIN

Clock to

Converter

Figure 15. DPLL Internal Functional Block Diagram

Example: MCLKIN/PLLCLKIN = 35.328 MHz. With NCO_DEF defaults at 64, 4.416-MHz clock is provided to

the ADC converter by the following equation:

4.416

+ 35.328

4

64

2

If NCO_DELTA [7:4] is set to – 1, NCO_DELTA [3:0] is set to 3, and NCO_DIV_DLY is set to 2 (NCO_DIV_DLY

should be the last register to be programmed), the internal divider will change to 63 three times. The change

programmed. The serial clock normally has a high of 14 ns and a low of 14 ns. The duty cycle of the SCLK

changes to 14 ns / 7 ns (14 ns / 21 ns if NCO_DELTA [7:4] = +1) during those jittering SCLK cycles.

Reprogramming of the register NCO_DIV_DELAY is needed if further adjustment is required.