TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

9

POST OFFICE BOX 655303

primary transfer data mapping

The data bit mapping of a primary transfer is shown in Figure 3. D15 – D2 bits of the SDR data stream are DAC

data. D1 is unused. D0 is the secondary transfer request bit. When a 1 is written to D0, the host is requesting

a secondary data transfer.

In the SDX data stream, D15 – D2 contain the ADC conversion data. D1 and D0 can be configured to reflect the

values of GPIO0 and GPIO1, when they are configured as inputs. D1 and D0 will contain zeroes if they are not

configured to reflect their corresponding GPIO pin value, or if the GPIO pin is configured as an output. To

configure D1 and D0 to reflect the GPIO values, the proper bit in the control register needs to be set.

D15 – D2

X

D0

Secondary Transfer Request

DAC Data

D15 – D2

D1

D0

GPIO1 and GPIO0 Status

A/D Data

SDR

SDX

GPIO1

GPIO0

Figure 3. Primary Transfer Data Bit Mapping

secondary transfer data mapping

Secondary serial communication is used to configure the device. The data bit mapping for a secondary transfer

is shown in Figure 4. The D14 – D10 bits of the SDR data, from the host, are the address bits of the control

register involved in the transfer. Bits D7 – D0 contain the data to the register. D15 needs to be set to zero all the

time.

A control register read-back function is not supported. As a result, there is no secondary FSX or SDX.

0

SDR (Write)

A4

A3

A2

A1

A0

D9 D8

D7

Register Address

Don’t Care

Data to the Register

D15

D0

Figure 4. Secondary Transfer Data Bit Mapping

example data transfers

Figure 5 and 6 show the timing relationship for SCLK, FSX, SDX, FSR, and SDR in a primary or secondary

communication. The update rate for TX and RX are controlled by pin configuration and register programming.

The timing sequence for this operation is as follows:

1.

FS is brought high and remains high for one SCLK period, then goes back low.

2.

A 16-bit word is transmitted from the ADC (SDX) and a 16-bit word is received for DAC conversion (SDR).

Figure 5 through 14 show the timing relationship of the data transfers with and without secondary request.