HT32F52230 datasheet(31/39 Pages) HOLTEK

31 / 39 page

Rev. 1.21

31 of 39

April 11, 2017

32-Bit ARM® Cortex™-M0+ MCU

HT32F52220/HT32F52230

SAR ADC

sample

Figure 7 ADC Sampling Network Model

The worst case occurs when the extremities of the input range (0V and VREF) are sampled

consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following

equation:

ADC

)

ln(







Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe

margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for

in this simple model.

If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations

between consecutive sampling phases, RS may be larger than the value indicated by the equation

above.

SCTM/GPTM Characteristics

Table 18 SCTM/GPTM Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fTM

Timer clock source for GPTM

—

MHz

tRES

Timer resolution time

—

fTM

fEXT

External signal frequency on

channel 1 ~ 4

—

1/2

fTM

RES

Timer resolution

—

bits

HT32F52230 Datasheet(PDF) 31 Page - Holtek Semiconductor Inc

HT32F52230 Datasheet(HTML) 31 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL