HT32F52230 datasheet(32/39 Pages) HOLTEK

32 / 39 page

Rev. 1.21

32 of 39

April 11, 2017

32-Bit ARM® Cortex™-M0+ MCU

HT32F52220/HT32F52230

I2C Characteristics

Table 19 I2C Characteristics

Symbol

Parameter

Standard Mode

Fast Mode

Fast Mode Plus

Unit

Min

Max

Min

Max

Min

Max

fSCL

Scl Clock Frequency

—

100

—

400

—

1000

kHz

tSCL(H)

Scl Clock High Time

4.5

—

1.125

—

0.45

—

μs

tSCL(L)

Scl Clock Low Time

4.5

—

1.125

—

0.45

—

μs

tFALL

Scl And Sda Fall Time

—

1.3

—

0.34

—

0.135

μs

tRISE

Scl And Sda Rise Time

—

1.3

—

0.34

—

0.135

μs

tSU(SDA)

Sda Data Setup Time

500

—

125

—

tH(SDA)

Sda Data Hold Time

—

tSU(STA)

Start Condition Setup Time

500

—

125

—

tH(STA)

Start Condition Hold Time

—

tSU(STO)

Stop Condition Setup Time

500

—

125

—

Note: 1. Guaranteed by design, not tested in production.

2. To achieve 100 kHz standard mode, the peripheral clock frequency must be higher than 2

MHz.

3. To achieve 400 kHz fast mode, the peripheral clock frequency must be higher than 8 MHz.

4. To achieve 1 MHz fast mode plus, the peripheral clock frequency must be higher than 20

MHz.

5. The above characteristic parameters of the I2C bus timing are based on: SEQ_FILTER = 01

and COMB_FILTER_En is disabled.

tSU(STA)

tH(STA)

tFALL

tSCL(L)

tRISE

tSCL(H)

tH(SDA)

tSU(SDA)

tSU(STO)

SCL

SDA

Figure 8 I2C Timing Diagrams

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