WM0011 datasheet(70/233 Pages) CIRRUS

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WM0011

Production Data

PD, Rev 4.1, August 2013

CCM_WKUP_CTRL

CHIP WAKEUP CONTROL REGISTER

Address = 0xF000_0030

Default value = 0x0001_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

BITS

FIELD

NAME

S/W

ACCESS

RESET

VALUE

FIELD

DESCRIPTION

WAIT_HIFI_SLP_ENA

0x0

HiFi EP

TM Sleep WAITI control

0 = Do not wait for HiFi WAITI to complete before entering Sleep mode

1 = Wait for HiFi WAITI to complete before entering Sleep mode

WKUP_RST_ENA

0x0

Selects whether a Wake-Up (exit from Sleep) triggers a Warm Reset

0 = Wake-Up does not trigger a Warm Reset

1 = Wake-Up triggers a Warm Reset

STATIC_VECT_SEL

0x0

Selects the DSP core boot vector following a Wake-Up transition.

Only valid when WKUP_RST_ENA=1.

0 = Boot to the primary static vector

1 = Boot to the alternate static vector

Table 25 CCM_WKUP_CTRL Register

CCM_DB_STBY – STANDBY DE-BOUNCE CONTROL REGISTER

The CCM_DB_STBY register configures the de-bounce circuit for the STANDBY

¯¯¯¯¯¯¯¯¯ input pin. The de-

bounced STANDBY

¯¯¯¯¯¯¯¯¯ is an input to the IRQC module, and also one of the DSP core interrupt inputs.

See “Interrupts” for details of the DSP core interrupts.

CCM_DB_STBY

STANDBY DE-BOUNCE CONTROL REGISTER

Address = 0xF000_0044

Default value = 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

BITS

FIELD

NAME

S/W

ACCESS

RESET

VALUE

FIELD

DESCRIPTION

STBY_DB_BYP

0x0

STANDBY

¯¯¯¯¯¯¯¯¯ de-bounce select

0 = De-bounce enabled

1 = De-bounce disabled (bypass)

30:24

Reserved

0x0

23:0

STBY_DB_CNT

0x00_

0000

STANDBY

¯¯¯¯¯¯¯¯¯ de-bounce time - sets the number of APBCLK clock cycles

for de-bouncing the STANDBY

¯¯¯¯¯¯¯¯¯ input pin.

Table 26 CCM_DB_STBY Register

WM0011 Datasheet(PDF) 70 Page - Cirrus Logic

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