WM0011 datasheet(89/233 Pages) CIRRUS

89 / 233 page

WM0011

Production Data

PD, Rev 4.1, August 2013

TIMER (TMR) MODULES

TIMER 1 - BASE ADDRESS 0xF001_0000

TIMER 2 - BASE ADDRESS 0xF001_0020

TIMER 3 - BASE ADDRESS 0xF001_0040

TIMER DESCRIPTION

The WM0011 provides three timers, which count up from 0, or count down from TMR_MAX_CNT. The

counters are enabled using the TMR_ENA bit, and count direction is selected using the TMR_DIR bit

(see Table 49).

The number of APBCLK clock cycles per count is determined by the TMR_PRESCALE register.

When TMR_PRESCALE = 00h, the module will count at the APBCLK clock rate.

The TMR_MODE bit enables a selectable external trigger to be used to start the timer count. The

TMC_INC bit configures the external trigger either as a ‘start’ trigger or as an alternate ‘clock’ signal.

When TMR_MODE=1 and TMR_INC=0, the count rate is controlled only by the external trigger (ie.

not by APBCLK).

The TMR_1SHOT bit selects whether the Timer automatically re-starts after the ‘end of count’

condition has been reached.

Note that the timer clock enable bit (TMR_CLK_ENA) is on the CCM_CLK_ENA register, and the

timer reset bit (TMR_SOFTRST_N) is in the CCM_SOFTRST register. Note that these signals are

common to all three Timer (TMR) modules.

Figure 23 Timer (TMR) Modules Block Diagram

WM0011 Datasheet(PDF) 89 Page - Cirrus Logic