WM0011 datasheet(29/233 Pages) CIRRUS

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WM0011

Production Data

PD, Rev 4.1, August 2013

POWER-ON AND RESET CONTROL

The WM0011 incorporates a number of different Reset mechanisms, which are summarised below.

Hardware Reset - this is controlled by the RESET

¯¯¯¯¯¯ input pin. When the RESET

¯¯¯¯¯¯ pin is asserted, the

chip is held in its reset condition, with all modules disabled and registers set to default. When the

RESET

¯¯¯¯¯¯ pin is de-asserted, the WM0011 will commence the boot sequence.

Warm Reset - this is controlled by the TOCDRST

¯¯¯¯¯¯¯¯¯ input pin, or by internal functions (Watchdog

timeout, PLL Lock status, or the Wake-Up FSM). Each of these triggers can be masked individually. If

any of the Warm Reset conditions is asserted (and unmasked), the Warm Reset will reset the core

functions and peripheral modules.

Software Reset - this function comprises individual reset control fields for each peripheral module.

POWER ON RESET

There is no Power-On Reset (POR) circuit for initialising the chip on power-up.

It is required that the RESET

¯¯¯¯¯¯ input pin is asserted (logic ‘0’) during power-up, and must remain

asserted until the power supply rails are within recommended operating conditions, and the CLKIN

reference is stable.

The WM0011 boot sequence will commence after the RESET

¯¯¯¯¯¯ pin has been de-asserted. When the

WM0011 is ready to commence software/configuration download, the IRQ

¯¯¯ output pin will be asserted

(logic ‘0’).

See “Boot Sequence Control” for details of the WM0011 boot sequence. Note that, on completion of

the boot sequence, the IRQ

¯¯¯ output pin will be de-asserted (logic ‘1’).

Note that, under default start-up conditions, the CLKIN input is selected as the clock source. The

Custom fuse settings, and/or PLL Configuration download, can be used to select the start-up clocking

configuration for different applications.

The Power-On Reset sequence is illustrated in Figure 8.

CLKIN

RESET

IRQ

DBVDD1

DBVDD2 / DBVDD3

AVDD / DCVDD

RESET input must be asserted

(logic 0) during power-up

Power supplies can be enabled in any order.

To prevent momentary drive on output pads, it

is recommended that DCVDD is enabled first.

CLKIN input must be held logic 0 until

after DBVDD1 has been applied

IRQ is asserted when the WM0011 is

ready for software download

CLKIN must be stable for at least 1 cycle before RESET

is de-asserted. The boot sequence commences after the

RESET input has been de-asserted.

Figure 8 Power-On Reset Sequence

WM0011 Datasheet(PDF) 29 Page - Cirrus Logic

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