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WM0011 Datasheet(PDF) 18 Page - Cirrus Logic |
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WM0011 Datasheet(HTML) 18 Page - Cirrus Logic |
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18 / 233 page  WM0011 Production Data w PD, Rev 4.1, August 2013 18 AUDIO INTERFACE (AIF) TIMING DIGITAL AUDIO INTERFACE – MASTER MODE Figure 2 AIF Interface Timing – Master Mode Test Conditions DCVDD=AVDD=1.2V, DBVDD1=DBVDD2=DBVDD3=1.8V, TA = +25°C, CLOAD=5pF (output pins) PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode AIFnBCLK cycle time tBCY 80 ns AIFnBCLK duty cycle 40 60 % AIFnLRCLK propagation delay from AIFnBCLK falling edge tLRD 0 15 ns AIFnTXDAT propagation delay from AIFnBCLK falling edge tDD 0 15 ns AIFnRXDAT setup time to AIFnBCLK rising edge tDSU 16.3 ns AIFnRXDAT hold time from AIFnBCLK rising edge tDH 16.3 ns Table 3 AIF Master Mode Timing Values Note the timing figures quoted in the table above are for full drive strength outputs; these timings are not guaranteed for reduced drive strength. |
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