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WM0011 Datasheet(PDF) 28 Page - Cirrus Logic

Part # WM0011
Description  General Purpose Low-Power Audio DSP
PDF  233 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM0011 Datasheet(HTML) 28 Page - Cirrus Logic

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WM0011
Production Data
w
PD, Rev 4.1, August 2013
28
JTAG MODULE
The WM0011 features an IEEE 1149.1 JTAG Test Access Port (TAP) controller module for chip
boundary scanning. The JTAG module also provides access to the On-Chip Debug (OCD) functions
for the DSP core. A de-bug server connects to the TAP through a host TAP interface, which is
typically an external device such as the USB2Demon™ from Macraigor Systems. All supported JTAG
probes are shown on the Tensilica website at http://www.tensilica.com/partners/jtag-probes/. Using
the JTAG TAP controller, users can access and control the software-visible state of the processor,
including:
Generate an interrupt to put the processor in the debug mode
Gain control of the processor upon any debug exception
Read and write any software-visible register and/or memory location
Resume normal mode of operation
The JTAG interface can be disabled on custom-programmed devices, to ensure device security.
When the JTAG module is disabled, the WM0011 will only execute software code that has been
securely authenticated.
The TAP interface consists of five signals listed below.
PIN NAME
DIRECTION
DESCRIPTION
TCK
Input
TAP clock
TMSDEBUG
Input
Input to TAP controller state machine
TMSDFT
Input
JTAG mode select input
TRST
¯¯¯¯¯
Input
Reset input (Active low) for initialisation of the TAP controller
TDI
Input
Selected serial instruction/data shift register input
TDO
Output
Selected serial instruction/data shift register tri-state output
Table 9 IEEE 1149.1 TAP Signals
For
more
detailed
information,
refer
to
the
‘Tensilica
On-Chip
Debugging
Guide’
(onchip_debug_guide.pdf).
ON-CHIP DEBUG MODULE
The Tensilica HiFi EP core has an On-Chip Debug (OCD) function that is accessed by the JTAG
module.
The OCD module may be reset by the JTAG debugger probe by asserting the TOCDRST
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ signal. This
signal may also optionally generate a warm reset of the chip.
For further details on the on-chip debug module, please refer to the Tensilica user guide for the on-
chip debug, ‘onchip_debug_guide.pdf’.



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