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WM0011 Datasheet(PDF) 36 Page - Cirrus Logic

Part # WM0011
Description  General Purpose Low-Power Audio DSP
PDF  233 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM0011 Datasheet(HTML) 36 Page - Cirrus Logic

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WM0011
Production Data
w
PD, Rev 4.1, August 2013
36
MESSAGE NAME
UART
(ASCII)
SPI SLAVE
DESCRIPTION
ROM_DBG_CODE_SECURE_MISMATCH
f
0x0FED0028
The decrypted image header does NOT match the
SHA result
ROM_DBG_CODE_ILLEGAL_DOWNLOAD
g
0x0FED0029
The USER has attempted a Code Download when
fuses are blank and JTAG is disabled
ROM_DBG_CODE_DL_FAIL
h
0x0FED002A
The code download has failed and will restart
ROM_DBG_BAD_SPI_FUSE_PKT
i
0x0FED002B
Invalid packet received when JTAG fuse is blank
ROM_DBG_BAD_SPI_PKT
j
0x0FED002C
SPI XFR length does NOT match packet length
N/A
k
0x0FED002D
Not Currently Used
N/A
l
0x0FED002E
Not Currently Used
N/A
m
0x0FED002F
Not Currently Used
N/A
n
0x0FED0030
Not Currently Used
N/A
o
0x0FED0031
Not Currently Used
ROM_DBG_SPI_ERR_RDOFL
p
0x0FED0032
SPI Read Overflow error reported by IP Packet is
discarded
ROM_DBG_SPI_ERR_UCLK
q
0x0FED0033
SPI Underclock error is reported by IP, Packet is
discarded
ROM_DBG_BAD_HDR_PKT
r
0x0FED0034
Header Packet does not contain correct # of bytes.
ROM_DBG_INVALID_PKT_TYPE
s
0x0FED0035
An unsupported packet type is received.
ROM_DBG_DATA_BEFORE_HDR
t
0x0FED0036
A Data packet is received without first receiving the
Header packet
ROM_DBG_FUSE_DL_FAIL_FUSES_PROG
D
u
0x0FED0037
A Custom Fuse image is received when fuses are
already programmed.
ROM_DBG_FUSE_DL_FAIL_BAD_CRC
v
0x0FED0038
Computed CRC in downloaded Fuse Packet is
incorrect.
ROM_DBG_INVALID_PLL_PKT
w
0x0FED0039
PLL packet with incorrect data length received.
ROM_DBG_CLEARING_PLL_OVERRIDE
x
0x0FED003A
PLL Unlock caused warm reset clearing error
before switching to PLL clock source
ROM_DBG_DATA_PACKET_ALIGN_ERR
y
0x0FED003B
Code Download packet has a length or address
that is not double word aligned
Table 11 Boot Status and Error Reporting
BOOT SEQUENCE FLOW DIAGRAMS
Figure 12, Figure 13 and Figure 14 illustrate the top level boot flow (Figure 12), boot packet
processing (Figure 13), and application validation (Figure 14).



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