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WM8224 Datasheet(PDF) 1 Page - Cirrus Logic |
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WM8224 Datasheet(HTML) 1 Page - Cirrus Logic |
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1 / 50 page  w WM8224 60MSPS 3-Channel AFE with Multiple Device Operation and Programmable Automatic Black Level Calibration WOLFSON MICROELECTRONICS plc Production Data, September 2013, Rev 4.2 Copyright 2013 Wolfson Microelectronics plc. DESCRIPTION The WM8224 is an analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 60MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. The output from each of these channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital data is available in a variety of output formats via the flexible data port. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. A programmable automatic Black-Level Calibration function is available to adjust the DC offset of the output data. A daisy chain feature allows multiple devices to operate together using the same control interface and output data bus. FEATURES 12 or 16-bit ADC, 40MSPS conversion rate 8 or 10-bit ADC, 60MSPS conversion rate Low power – 360 mW typical 3.3V single supply operation 3 channel operation Daisy Chain feature for multiple device use Correlated double sampling Programmable gain (9-bit resolution) Programmable offset adjust (8-bit resolution) Flexible clamp timing Programmable clamp voltage Internally generated voltage references Automatic Black Level Calibration 32-lead QFN package Serial control interface APPLICATIONS Digital Copiers USB2.0 compatible scanners Multi-function peripherals High-speed CCD/CIS sensor interface BLOCK DIAGRAM RINP DATA O/P PORT SEN VSMP MCLK VRLC/VBIAS SDI SCK TIMING CONTROL CLMP RLC V S R S BINP GINP VRX VRT OEB VRB RLC RLC CDS CDS CDS RLC DAC 16- BIT ADC AGND1 DGND DVDD OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] AGND2 M U X VREF/BIAS + PGA I/P SIGNAL POLARITY ADJUST PGA OFFSET DAC PGA OFFSET DAC + + + + + I/P SIGNAL POLARITY ADJUST I/P SIGNAL POLARITY ADJUST AVDD WM8224 RSMP OP[9] OFFSET DAC OP[0] OP[1] DSLCT SERIAL CONTROL INTERFACE BLACK LEVEL CALIBRATION + OP[11]/SDO OP[10] |
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