WM8224 datasheet(16/50 Pages) CIRRUS

16 / 50 page

WM8224

Production Data

PD, Rev 4.2, September 2013

INTERNAL POWER ON RESET CIRCUIT

Figure 10 Internal Power On Reset Circuit Schematic

The WM8224 includes an internal Power-On-Reset Circuit, as shown in Figure 10, which is used to

reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and

monitors DVDD. It asserts PORB low if AVDD or DVDD is below a minimum threshold.

DVDD

AVDD

pord_on

DGND

AGND

Internal POR active

Device Ready

Internal

POR active

No Power

POR

Undefined

pora_off

pora

INTERNAL PORB

Figure 11 Typical Power up Sequence where AVDD is Powered before DVDD

Figure 11 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises

above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is

asserted low and the chip is held in reset. In this condition, all writes to the control interface are

ignored. Now AVDD is at full supply level. Next DVDD rises to Vpord_on and PORB is released high

and all registers are in their default state and writes to the control interface may take place.

On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the

minimum threshold Vpora_off.

Figure 12 Typical Power up Sequence where DVDD is Powered before AVDD

WM8224 Datasheet(PDF) 16 Page - Cirrus Logic