WM8224 datasheet(22/50 Pages) CIRRUS

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WM8224

Production Data

PD, Rev 4.2, September 2013

128

256

384

512

Gain Code (PGA[8:0])

0.5

1.5

2.5

3.5

128

256

384

512

Gain Code (PGA[8:0])

Max i/p Voltage

LOWREFS=0

Max i/p Voltage

LOWREFS=1

Figure 17 PGA Gain Characteristic

Figure 18 Peak Input Voltage to Match ADC Full-scale Range

ADC INPUT BLACK LEVEL ADJUST

The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRT-

VRB]).

For negative-going input video signals, a black level (zero differential) output from the PGA should be

offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output

code of FFFF (hex) from the WM8224 for zero input. If code zero is required for zero differential input

then the INVOP bit should be set.

For positive going input signals the black level should be offset to the bottom of the ADC range by

setting PGAFS[1:0]=11. This will give an output code of 0000 (hex) from the WM8224 for zero input.

Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01. Zero differential

input voltage gives mid-range ADC output, 7FFF (hex).

WM8224 Datasheet(PDF) 22 Page - Cirrus Logic