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WM8224 Datasheet(PDF) 36 Page - Cirrus Logic |
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WM8224 Datasheet(HTML) 36 Page - Cirrus Logic |
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36 / 50 page  WM8224 Production Data w PD, Rev 4.2, September 2013 36 Figure 32 Control Interface Register Write A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word = XXXXXXXX). REGISTER READ-BACK Figure 33 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (id1, id0, a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register in the addressed device to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[11], and readback will override a high- impedance output on this pin. The next word may be read in to SDI while the previous word is still being output on SDO. Figure 33 Serial Interface Register Read-back MULTIPLE DEVICE OPERATION Up to 3 WM8224 devices can be configured to share common serial interfaces and output data buses. In order to accommodate multiple devices on a shared output bus a higher number of MCLKs per VSMP are required. When multiple devices are being used the WM8224 can be configured so that the outputs are high impedance apart from during valid data output by setting the AUTOZ register bit to 1. [Note that AUTOZ should not be used if the MCLK : VSMP ratio is 1:1.] The output of each device can be staggered by adjusting the latency via the OPDEL[3:0] register bits, allowing multiple devices to share the same output bus. BUS CONTENTION In 3 channel mode, an MCLK:VSMP ratio of 8:1 (2 devices) or 12:1 (3 devices) is recommended to give an spare MCLK cycle in which to allow the output data pins to transition in and out of a high impedance state. However an MCLK:VSMP ratio of 6:1 (2 devices) or 9:1 (3 devices) can be used, but care must be taken with output timing to prevent bus contention. |
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