WM8224 datasheet(35/50 Pages) CIRRUS

35 / 50 page

WM8224

Production Data

PD, Rev 4.2, September 2013

REFERENCES

The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins

VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and

also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin

VRLC/VBIAS.

The ADC references can be switched from the default values (VRT=2.05V, VRB=1.05V, ADC input

range=2V) to give a smaller ADC reference range (VRT=1.85V, VRB=1.25V, ADC input range=1.2V)

under control of the LOWREFS register bit. Setting LOWREFS=1 allows smaller input signals to be

accommodated.

Note:

When LOWREFS = 1 the output of the RLCDAC will scale if RLCDACRNG = 1. The max output from

RLCDAC will change from 2.05 to 1.85V and the step size will proportionally reduce.

POWER MANAGEMENT

Power management for the device is performed via the Control Interface. By default the device is fully

enabled. The EN bit allows the device to be fully powered down when set low. Individual blocks can

be powered down using the bits in Setup Register 5. When in MONO or TWOCHAN mode the

unused input channels are automatically disabled to reduce power consumption.

Note:

It is recommended that if the clocks are removed from the device, the device should be

powered down using the EN bit in Setup Reg 1.

It is recommended that when the device is powered up after powered down using the EN bit

Setup Reg 1, PGA gain setting should be set to default. Alternatively if PGA gain is not

default, the following sequence can be applied after powered up using EN bit.

Setup Reg 6, bit[0] (RESET_NOREG) =1

ii.

Setup Reg 6, bit[0] (RESET_NOREG) = 0

Note2 is also recommended when MONO or TWOCHAN is changed.

CONTROL INTERFACE

The internal control registers are programmable via the serial digital control interface. The register

contents can be read back via the serial interface on pin OP[11]/SDO.

It is recommended that a software reset is carried out after the power-up sequence, before writing to

any other register. This ensures that all registers are set to their default values (as shown in Table

15).

DEVICE IDENTIFICATION

Up to 3 WM8224 devices can share a common set of serial interface pins. Each device on the

common interface bus must be given a different device ID. The device ID is set by the input pin

DSLCT as shown in Table 11.

DSLCT

DEVICE ID

(ID[1:0])

Table 11 Device Identification

Figure 32 shows sequence of operations for performing a register write. Three pins, SCK, SDI and

SEN are used for the control interface. An eight-bit address (id1, id0, a5, 0, a3, a2, a1, a0) is clocked

in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB

first. The device ID bits indicate which device is being written to on a shared control bus. A register

write with device ID set to 11 writes data to all devices on the common bus. Setting address bit a4 to

0 indicates that the operation is a register write. Each bit is latched on the rising edge of SCK. When

the data has been shifted into the device, a rising edge on the SEN pin transfers the data to the

appropriate internal register.

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