WM8310 datasheet(51/291 Pages) CIRRUS

51 / 291 page

Pre-Production

WM8310

PP, May 2012, Rev 3.1

In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.

This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if

desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an

integer value, as illustrated in the following example:

If N.K = 8.192, then K = 0.192.

Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex).

For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations

yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order that N.K is a

non-integer value. Care must always be taken to ensure that the FLL operating frequency, FVCO, is

within its recommended limits of 90-100 MHz.

The register fields that control the FLL are described in Table 20.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R16530 (4092h)

FLL Control 1

FLL_FRAC

Fractional enable

0 = Integer Mode

1 = Fractional Mode

Integer mode offers reduced power

consumption. Fractional mode

offers best FLL performance,

provided also that N.K is a non-

integer value.

FLL_ENA

FLL Enable

0 = Disabled

1 = Enabled

Note - this bit is reset to 0 when

the OFF power state is entered.

R16531 (4093h)

FLL Control 2

13:8

FLL_OUTDIV

[5:0]

000000

FOUT clock divider

000000 = Reserved

000001 = Reserved

000010 = Reserved

000011 = 4

000100 = 5

000101 = 6

…

111110 = 63

111111 = 64

(FOUT = FVCO / FLL_OUTDIV)

6:4

FLL_CTRL_R

ATE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended

value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

110 = FVCO / 7

111 = FVCO / 8

Recommended that this register is

not changed from default.

2:0

FLL_FRATIO

[2:0]

000

FVCO clock divider

000 = 1

001 = 2

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