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WM8310 Datasheet(PDF) 75 Page - Cirrus Logic

Part # WM8310
Description  Processor Power Management Subsystem
PDF  291 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8310 Datasheet(HTML) 75 Page - Cirrus Logic

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Pre-Production
WM8310
w
PP, May 2012, Rev 3.1
75
The Enable and Status register bits for the External Power Enable (EPE) Controls are defined in
Table 35.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16464 (4050h)
DCDC Enable
7
EPE2_ENA
0
EPE2 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in EPE2_STS)
6
EPE1_ENA
0
EPE1 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in EPE1_STS)
R16466 (4052h)
DCDC Status
7
EPE2_STS
0
EPE2 Status
0 = Disabled
1 = Enabled
6
EPE1_STS
0
EPE1 Status
0 = Disabled
1 = Enabled
Table 35 External Power Enable (EPE) Control
15.12.2 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL
The register controls for configuring the DC-DC synchronous buck converters 1-3 are defined in Table
36.
Note that the DCm_ON_SLOT fields and the 5 MSBs of DCm_ON_VSEL may also be stored in the
integrated OTP memory. See Section 14 for details.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16470 (4056h)
DC1 Control 1
15:14
DC1_RATE
[1:0]
10
DC-DC1 Voltage Ramp rate
00 = 1 step every 32us
01 = 1 step every 16us
10 = 1 step every 8us
11 = Immediate voltage change
12
DC1_PHASE
0
DC-DC1 Clock Phase Control
0 = Normal
1 = Inverted
9:8
DC1_FREQ
[1:0]
00
DC-DC1 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
7
DC1_FLT
0
DC-DC1 Output float
0 = DC-DC1 output discharged when
disabled
1 = DC-DC1 output floating when
disabled
5:4
DC1_SOFT_
START [1:0]
00
DC-DC1 Soft-Start Control
(Duration in each of the 8 startup current
limiting steps.
00 = 32us steps
01 = 64us steps
10 = 128us steps
11 = 256us steps



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