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WM8310 Datasheet(PDF) 89 Page - Cirrus Logic |
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WM8310 Datasheet(HTML) 89 Page - Cirrus Logic |
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89 / 291 page  Pre-Production WM8310 w PP, May 2012, Rev 3.1 89 15.12.5 EXTERNAL POWER ENABLE (EPE) CONTROL The register controls for configuring the External Power Enable (EPE) outputs are defined in Table 41. Note that the EPE1_ON_SLOT and EPE2_ON_SLOT fields may also be stored in the integrated OTP memory. See Section 14 for details. ADDRESS BIT LABEL DEFAULT DESCRIPTION R16486 (4066h) EPE1 Control 15:13 EPE1_ON_S LOT [2:0] 000 EPE1 ON Slot select 000 = Do not enable 001 = Enable in Timeslot 1 010 = Enable in Timeslot 2 011 = Enable in Timeslot 3 100 = Enable in Timeslot 4 101 = Enable in Timeslot 5 110 = Controlled by Hardware Enable 1 111 = Controlled by Hardware Enable 2 12:11 EPE1_HWC _SRC [1:0] 00 EPE1 Hardware Control Source 00 = Disabled 01 = Hardware Control 1 10 = Hardware Control 2 11 = Hardware Control 1 or 2 8 EPE1_HWC ENA 0 EPE1 Hardware Control Enable 0 = EPE1 is controlled by EPE1_ENA (Hardware Control input(s) are ignored) 1 = EPE1 is controlled by HWC inputs (Hardware Control input(s) force EPE1 to be de-asserted) 7:5 EPE1_SLP_ SLOT [2:0] 000 EPE1 SLEEP Slot select 000 = No action 001 = Disable in Timeslot 5 010 = Disable in Timeslot 4 011 = Disable in Timeslot 3 100 = Disable in Timeslot 2 101 = Disable in Timeslot 1 110 = No action 111 = No action R16487 (4067h) EPE2 Control 15:13 EPE2_ON_S LOT [2:0] 000 Same as EPE1 12:11 EPE2_HWC _SRC [1:0] 00 Same as EPE1 8 EPE2_HWC ENA 0 Same as EPE1 7:5 EPE2_SLP_ SLOT [2:0] 000 Same as EPE1 Table 41 External Power Enable (EPE) Control 15.12.6 MONITORING AND FAULT REPORTING The overvoltage, undervoltage and high current status registers are defined in Table 42. ADDRESS BIT LABEL DEFAULT DESCRIPTION R16468 (4054h) DCDC UV Status 13 DC2_OV_ST S 0 DC-DC2 Overvoltage Status 0 = Normal 1 = Overvoltage 12 DC1_OV_ST S 0 DC-DC1 Overvoltage Status 0 = Normal 1 = Overvoltage |
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