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AD9249 Datasheet(PDF) 9 Page - Analog Devices |
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AD9249 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 37 page  AD9249 Data Sheet Rev. 0 | Page 8 of 36 Timing Diagrams Refer to the Memory Map Register Descriptions section for SPI register setting of output mode. Figure 3. Wordwise DDR, 1× Frame, 14-Bit Output Mode (Default) Figure 4. Wordwise DDR, 1× Frame, 12-Bit Output Mode DCO–1, DCO–2 DCO+1, DCO+2 FCO–1, FCO–2 FCO+1, FCO+2 D–x1, D–x2 D+x1, D+x2 VIN±x1, VIN±x2 CLK– CLK+ MSB N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D9 N – 17 D8 N – 17 D7 N – 17 D6 N – 17 D5 N – 17 D4 N – 17 D3 N – 17 D2 N – 17 D0 N – 17 D1 N – 17 D12 N – 16 MSB N – 16 N – 1 tA tEH tCPD tFCO tPD tDATA tFRAME tEL N VIN±x1, VIN±x2 CLK– CLK+ MSB N – 17 D10 N – 17 D9 N – 17 D8 N – 17 D7 N – 17 D6 N – 17 D5 N – 17 D4 N – 17 D3 N – 17 D2 N – 17 D1 N – 17 D0 N – 17 D10 N – 16 MSB N – 16 N – 1 N tDATA tFRAME tFCO tPD tCPD tEH tA tEL DCO–1, DCO–2 DCO+1, DCO+2 FCO–1, FCO–2 FCO+1, FCO+2 D–x1, D–x2 D+x1, D+x2 |
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