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Data Sheet

AD9249

Rev. 0 | Page 33 of 36

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

Bits[6:4] determine at which phase of the external clock the

sampling occurs. This is applicable only when the clock divider

is used. It is prohibited to select a value for Bits[6:4] that is

greater than the value of Bits[2:0], Register 0x0B. See Table 19

for more information.

Table 19. Input Clock Phase Adjust Options

Input Clock Phase

Adjust, Bits[6:4]

Number of Input Clock Cycles

of Phase Delay

000 (Default)

001

010

011

100

101

110

111

Bits[3:0]—Output Clock Phase Adjust

See Table 20 for more information.

Table 20. Output Clock Phase Adjust Options

Output Clock, Phase

Adjust, Bits[3:0]

DCO Phase Adjustment

(Degrees Relative to D±x Edge)

0000

0001

0010

120

0011 (Default)

180

0100

240

0101

300

0110

360

0111

420

1000

480

1001

540

1010

600

1011

660

Resolution/Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device

(that is, establish lower power) for applications that do not require

full sample rate. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is set to 1.

This function does not affect the sample rate; it affects the

maximum sample rate capability of the ADC, as well as the

resolution.

User I/O Control 2 (Register 0x101)

Bits[7:1]—Open

Bit 0—SDIO Pull-Down

Set Bit 0 = 1 to disable the internal 30 kΩ pull-down on the

SDIO/DFS pin. This feature limits loading when many devices

are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Set Bit 3 = 1 to power down the internal VCM generator. This

feature is used when applying an external reference.

Bits[2:0]—Open

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