AD9249 datasheet(28/37 Pages) AD

28 / 37 page

Data Sheet

AD9249

Rev. 0 | Page 27 of 36

HARDWARE INTERFACE

The pins described in Table 15 comprise the physical interface

between the user programming device and the serial port of the

AD9249. The SCLK/DTP pin (SCLK functionality) and the CSB1

and CSB2 pins function as inputs when using the SPI interface.

The SDIO/DFS pin (SDIO functionality) is bidirectional,

functioning as an input during write phases and as an output

during readback.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB1 and CSB2 signals, and the SDIO signal

are typically asynchronous to the ADC clock, noise from these

signals can degrade converter performance. If the on-board SPI

bus is used for other devices, it may be necessary to provide

buffers between this bus and the AD9249 to prevent these

signals from transitioning at the converter inputs during critical

sampling periods.

Some pins serve a dual function when the SPI interface is not

being used. When the pins are strapped to DRVDD or ground

during device power-on, they are associated with a specific

function. Table 13 and Table 14 describe the strappable

functions supported on the AD9249.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin

serve as standalone CMOS-compatible control pins. When the

device is powered up, it is assumed that the user intends to use the

pins as static control lines for the output data format, output

digital test pattern, and power-down feature control. In this

mode, connect CSB1 and CSB2 to AVDD, which disables the

serial port interface.

When the device is in SPI mode, the PDWN pin (if enabled)

remains active. For SPI control of power-down, set the PDWN pin

to its inactive state (low).

SPI ACCESSIBLE FEATURES

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described further in

the AN-877 Application Note, Interfacing to High Speed ADCs via

SPI. The AD9249 device-specific features are described in detail

in the Memory Map Register Descriptions section following

Table 17, the external memory map register table.

Table 16. Features Accessible Using the SPI

Feature Name

Description

Power Mode

Allows the user to set either power-down mode

or standby mode

Clock

Allows the user to access the DCS, set the clock

divider, set the clock divider phase, and enable

the sync function

Offset

Allows the user to digitally adjust the converter

offset

Test I/O

Allows the user to set test modes to have

known data on output bits

Output Mode

Allows the user to set the output mode

Output Phase

Allows the user to set the output clock polarity

ADC Resolution

and Speed Grade

Allows scalable power consumption options

based on resolution and speed grade selection

AD9249 Datasheet(PDF) 28 Page - Analog Devices

AD9249 Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL